UCIe-S PHY for Standard Package (x16) in TSMC N3E, North/South Orientation

The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI, and networking applications. The PHY’s flexible architecture supports standard and advanced package technologies and allows up to 12.9Tbps/mm of data to travel at data rates up to 40Gbps. It supports widely used AMBA protocols such as AXI and CHI C2C in streaming mode and standards-based protocols such as PCI Express and CXL. The IP offers maximum performance with low BER, minimum latency, and implementation flexibility. The UCIe PHY IP delivers high energy efficiency with an optimized architecture using a single reference clock feature, low-voltage signaling, and hardware-based initialization. The mission mode integrated signal integrity monitors and comprehensive test and repair capabilities ensure die, die-to-die, and multi-die package health from in-design to in-field. Robust die-to-die link operation is ensured with embedded training and calibration algorithms. The PHY is compliant with the latest release of the UCIe specification, ensuring successful interoperability between heterogeneous dies. The UCIe PHY IP along with the Controller IP and Verification IP deliver a complete solution for die-to-die connectivity in multi-die packages.

• Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
• Compliant with the latest UCIe specification
• Integrated signal integrity monitors and comprehensive test and repair features
• Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
• Supports standard packaging technologies such as organic substrate and laminate
• Hardware-based initialization & sideband vendor message support
• 100 MHz single reference clock architecture
• Supports on-chip interconnect fabrics including AXI, CHI C2C, CXS, PCIe, CXL, and streaming