Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
Variable FFT (run time choice of FFT size)
This FFT circuit employs unique architectural characteristics, different than any other FFT implementation.
LTE Single Carrier FFT Circuit
Centar's DFT circuit can perform all 35 transform sizes needed to implement the LTE SC-FDMA protocols.
The DVB-S2X decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 100 MSymbols/s on FPGAs.
ASIP-2 Programmable Filter Engine
Application Specific Instruction Set Processors (ASIPs) possess an instruction set which is tailored to benefit a specific applic…
WCDMA Release 9 compliant Viterbi Decoder
The Lekha IP – 3GPP WCDMA Viterbi Decoder IP Core V1.0 addresses the implementation of the Viterbi Decoder defined as part of the…
Constant False Alarm Rate Processor (CFAR)
The eSi-CFAR is an high throughput Constant False Alarm Rate (CFAR) IP core, whose main application area is automotive driver ass…
High bit rate Turbo Decoder core for 3GPP LTE/ LTE A
The Lekha IP – 3GPP LTE Turbo Decoder IP Core V1.0 addresses the decoder implementation for the turbo coded transport channel com…
LMS Adaptive Channel Equalizer
The AH1001_LEQ LMS Adaptive Channel Equalizer (LEQ) FPGA core provides a 17-tap Least Mean Squares (LMS) signed-error adaptive Ch…
32-bit Floating-point Square-root IP Core
High-speed fully pipelined 32-bit floating-point square-root function based on the IEEE 754 standard.
Generic Open Source Viterbi Decoder
Convolutional codes are widely adopted in wireless communication systems for forward error correction.
The BCH decoder has four main functional blocks along with memory blocks.
Highest code density, Low Power 32-bit Processor with optional DSP
The Beyond BA22 32-bit processor offers the highest code density of any processor in its class, reducing die size and memory requ…
256 bit per clock LZ4 Decompressor Core
Ultra low-Latency Single-Engine Decompressor Core
The SiFive® Performance™ P570 Gen 3 brings fully out-of-order support coupled with support for the most comprehensive set of RVA2…
Compact and low energy consumption to provide the performance you need in radar, lidar, and communications processing at ultra-low area and energy cost
RISC-V-Based, Open Source AI Accelerator for the Edge
Coral NPU is a machine learning (ML) accelerator core designed for energy-efficient AI at the edge.
License our analog in-memory compute macros (e.g., 32×32 X1 crossbars) for integration into your ASIC or SoC.
Shaped Offset Quadrature Phase Shift Keying - Telemetry Group (SOQPSK-TG) is a type of QPSK/OQPSK modulation.
LZ4SNP-C is a custom hardware implementation of a lossless data compression engine that complies with the LZ4 and Snappy compress…
The FFT4T core implements a 128 point complex FFT and IFFT over 12 data streams in hardware.