The MixedRadix FFT IP Core uses a modular combination of radix2, 3, 5, and 7 Fast Fourier Transform (FFT) pipelined engines to pr…
- Filters Transforms
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
The MixedRadix FFT IP Core uses a modular combination of radix2, 3, 5, and 7 Fast Fourier Transform (FFT) pipelined engines to pr…
LatticeMico32 Open, Free 32-Bit Soft Processor
The LatticeMico32™ is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensin…
Soft errors occur when high-energy charged particles alter the stored charge in a memory cell in an electronic circuit.
The CMS0014 DVB-S2 (A)PSK Demodulator is a high-performance (A)PSK demodulator core intended for DVB-S2 and DVB-S2X forward link …
Interleaving is a technique commonly used in communication systems to overcome correlated channel noise such as burst error or fa…
Dynamic Block Reed-Solomon Encoder
Reed-Solomon codes are used to perform Forward Error Correction (FEC).
Dynamic Block Reed-Solomon Decoder
Reed-Solomon codes are used to perform Forward Error Correction (FEC).
Convolutional encoding is a process of adding redundancy to a signal stream to provide error correction capability.
Turbo coding is an error correction technique widely used in the communications industry.
Turbo coding is an error correction technique widely used in the communications industry.
Distributed Arithmetic FIR (DA-FIR) Filter Generator
The Lattice Distributed Arithmetic Finite Impulse Response (DA-FIR) Filter Generator IP implements a configurable, multi-channel …
Viterbi decoding is an efficient algorithm for decoding convolutionally encoded sequences corrupted by channel noise back to the …
Lattice's FFT Compiler offers forward and inverse Fast Fourier Transforms for point sizes from 64 to 16384.
Register, Configuration and Control Bus
A2R provides an interconnection mechanism between control registers in an ASIC design and any number of control devices; CPUs, de…
Single Precision IEEE-754 complete FPU
The A2F is a fully synthesizable module implemented in Verilog RTL.
The CMS0006 Universal QAM Demodulator is a 4th generation design that exploits Commsonic’s experience of QAM and OFDM systems for…
The CMS0004 Universal QAM/PSK Modulator is a flexible, high-performance, linear modulator core designed for a wide range of broad…
The FFT is factored into Radix-4 Butterfly operations.
Reed Solomon Codec (Errors-only)
The CMS0007 Reed Solomon Codec provides ultimate flexibility in its operation and build.
The J5 is a core cell design of an application specific signal processor which performs both Trusurround(TM) and SRS® 3-D audio v…