Scaling AI from Edge to Data Center with SiFive RISC-V Vectors
AI with Sally
In this podcast, John Simpson, senior principal architect for SiFive’s Intelligence products, talks about how RISC-V processors are designed to support AI workloads from the edge to the data center.
Related Semiconductor IP
- Multi-core capable 32-bit RISC-V CPU with vector extensions
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 8-stage dual issue, in-order, superscalar processor with dual vector processing units (1024-bit VLEN/512-bit DLEN)
- Multi-core capable RISC-V processor with vector extensions
- RISC-V Debug & Trace IP
Related Videos
- Arm: Scaling AI Compute from Edge to Cloud
- RISC-V: Spanning Datacenter to Edge
- BrainChip Expands IP Business Model with AKD1500 Production to Accelerate Edge AI Deployment
- Software to silicon with RISC-V for Physical AI
Latest Videos
- Can AI Be Trusted? Synopsys on Agentic AI and Autonomous Engineering
- Caliptra Silicon Root of Trust in BMC SoCs
- UALink 2.0 Specification Update: Advancing Accelerator Interconnect Technology for AI Workloads
- Silicon IP for Your GPU??? | Oxmiq Labs
- The Future of AI Scale-Up: Latest Advancements in UALink Technology