RISC-V Design Innovations with Custom Extensions
Andes and Synopsys present a ‘software first’ design flow using virtual platforms/prototypes allows RISC-V developers to explore new hardware configuration options with application SW workloads and full OS support.
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Videos
- How to design robust SoC with ESD and power management IP
- Architecture Exploration of SoC with Arm IP using VisualSim Architect
- Scaling AI from Edge to Data Center with SiFive RISC-V Vectors
- Secure RISC-V Processor for Root of Trust
Latest Videos
- Powering the AI Supercycle: Design for AI and AI for Design - Anirudh Devgan
- Scaling AI from Edge to Data Center with SiFive RISC-V Vectors
- Paving the Road to Datacenter-Scale RISC-V
- Enhancing Data Center Architectures with PCIe® Retimers, Redrivers and Switches
- How UCIe 3.0 Redefining Chiplet Architecture: From Protocol to Platform