RISC-V Design Innovations with Custom Extensions
Andes and Synopsys present a ‘software first’ design flow using virtual platforms/prototypes allows RISC-V developers to explore new hardware configuration options with application SW workloads and full OS support.
Related Semiconductor IP
- USB-C Power Delivery IP Core
- Configurable Multi-Channel DMA Controller
- Samsung Foundry 4nm 1V8 GPIO I3C
- Root-of-Trust IP - High-Assurance Security for Advanced and Regulated Applications
- Root-of-Trust IP - Enhanced-Assurance, Configurable Security for Scalable Semiconductor Designs
Related Videos
- How to design robust SoC with ESD and power management IP
- Architecture Exploration of SoC with Arm IP using VisualSim Architect
- Scaling AI from Edge to Data Center with SiFive RISC-V Vectors
- Software to silicon with RISC-V for Physical AI
Latest Videos
- Cadence UCIe at 64 GT/s in Silicon: Why It Matters for Your Next Chiplet Design
- Can AI Be Trusted? Synopsys on Agentic AI and Autonomous Engineering
- Caliptra Silicon Root of Trust in BMC SoCs
- UALink 2.0 Specification Update: Advancing Accelerator Interconnect Technology for AI Workloads
- Silicon IP for Your GPU??? | Oxmiq Labs