Software to silicon with RISC-V for Physical AI
Nitin Dahad of EE Times moderates a panel with Sameer Wasson, CEO of MIPS, by GF, and Andrea Gallo, CEO of RISC-V International for a conversation on how the industry must rethink chip design for Agentic AI. Topics covered:
- GlobalFoundries’ acquisition of MIPS and the recent acquisition of the Synopsys ARC Processor IP solutions business and what it means for customers
- Why RISC-V is becoming the default ISA for new silicon designs
- The shift to software-first, workload-optimized architectures
- How MIPS Atlas Explorer virtual platforms shortens time to revenue
Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
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- Panel with Arteris, GlobalFoundries, Tenstorrent: RISC-V Ecosystem Growth for Physical AI
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- Scaling AI from Edge to Data Center with SiFive RISC-V Vectors
- Hardware Innovation in the World's First RISC-V 50 TOPS AI Compute for Mass Production Development