Software to silicon with RISC-V for Physical AI
Nitin Dahad of EE Times moderates a panel with Sameer Wasson, CEO of MIPS, by GF, and Andrea Gallo, CEO of RISC-V International for a conversation on how the industry must rethink chip design for Agentic AI. Topics covered:
- GlobalFoundries’ acquisition of MIPS and the recent acquisition of the Synopsys ARC Processor IP solutions business and what it means for customers
- Why RISC-V is becoming the default ISA for new silicon designs
- The shift to software-first, workload-optimized architectures
- How MIPS Atlas Explorer virtual platforms shortens time to revenue
Related Semiconductor IP
- RISC-V Display Connectivity Subsystem (DCS)
- RISC-V IOPMP IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
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