Reclaiming lost yield through methodical power integrity optimization
Christian Petersen, Teklatech A/S
EETimes (4/1/2013 10:32 AM EDT)
As designs are moving to 28nm and beyond, designers fully experience the effects of the much higher power density and diminishing effectiveness of decoupling capacitances at these geometries: failures due to dynamic power noise integrity issues is a significant contributor to yield loss in many designs. Synchronous switching and increasing di/dt at advanced process nodes (Figure 1) makes it increasingly challenging for designers to deal with on-chip dynamic voltage drop (DVD) and high frequency electromagnetic interference (EMI). And neither is to be taken lightly; studies have shown DVD fluctuations introduce sizable gate delays causing timing-related yield loss, and EMI from digital switching similarly cause mixed-signal yield loss due to compromised noise integrity.
To read the full article, click here
Related Semiconductor IP
- EXT-64-2048 GPU
- Mesochronous Bridge for PCIe/CXL
- AI-native GPU
- OpenGMSL Verification IP
- OpenGMSL Leaf IP
Related Articles
- A modeling approach for power integrity simulation in 3D-IC designs
- Leakage power optimization for 28nm and beyond
- Effective Optimization of Power Management Architectures through Four standard "Interfaces for the Distribution of Power"
- Power Optimization using Multi BIT flops and MIMCAPs in 16nm technology and below
Latest Articles
- Can Agents Design Better Chips with a Higher Level Abstraction?
- FlexSpIM: An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Hybrid Stationarity
- MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators
- Analog Pin Directionality as an Exfiltration Attack Surface in Mixed-Signal ICs
- SIMT-Aware Lockstep Verification and Functional-Coverage Closure Methodology for an Open-Source RISC-V GPGPU: A UVM 1.2 Environment