What’s the number of ASIC versus FPGA design starts?
Clive Maxfield, EETimes
3/20/2011 12:32 PM EDT
It is not uncommon to see an article or read a paper that says something like “In 2010 there were 2,500 ASIC design starts versus 90,000 FPGA design starts.” And we say to ourselves: “Well, that’s jolly interesting.” And then we quote these values to each other in conversations at the water cooler and use them in our own papers and articles, but where do these numbers actually come from and how accurate are they?
Of course we all know that there are fewer ASIC design starts today as compared to say five or ten years ago. This is primarily because designing ASICs at the latest and greatest technology nodes is an increasingly complex, resource-intensive, time-consuming, and expensive hobby.
It’s also common knowledge that there are more FPGA design starts today than there were five and ten years ago. In addition to the fact that the use of electronics is increasing dramatically in almost all walks of life, this is primarily due to the fact that today’s FPGAs have higher capacity and higher performance coupled with lower power consumption (relatively speaking), all of which means that FPGAs can now play in applications and markets that were previously “owned” by ASICs and other devices.
To read the full article, click here
Related Semiconductor IP
- 100-10Gbps Ethernet MAC Controller
- SD Card Controller
- AXI4 Memory Controller IP Core
- AXI-Lite I2C Controller Core
- LVDS Transceiver IP core
Related Articles
- An Outline of the Semiconductor Chip Design Flow
- The rise of FPGA technology in High-Performance Computing
- Understanding the Importance of Prerequisites in the VLSI Physical Design Stage
- The role of cache in AI processor design
Latest Articles
- LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation
- Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors
- Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library
- A 105 MS/s 4.18 nJ/inference 0.765 mm² Mixed-Signal Streaming ML Engine for Wireless Baseband in 12LP+ FinFET
- Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains