Virtual prototyping boosts model-driven Design for Six Sigma methodology: Part 3 of 3 - Design example: Electronic throttle control
By Darrell Teegarden, Mentor Graphics Corporation
Automotive DesignLine (04/24/08, 03:44:00 PM EDT)
Part 1 of this 3-part series described how a model-driven development process and virtual prototyping tools help address the challenges of implementing a DFSS methodology in a complex automotive electronics development process.
Part 2 details how a model-driven development process is integrated with a DFSS methodology to provide a more efficient way to ensure that customer critical-to-quality (CTQ) requirements are met in the final product.
Imagine all the variables that can affect the performance of your design—from part tolerances to process variations and environmental conditions. Testing a physical prototype for even a fraction of these factors can be expensive, time-consuming, and error-prone. However, you can significantly cut the costs of testing by simulating with virtual prototypes.
A model-driven Design for Six Sigma (DFSS) approach provides an effective structure for managing a complex development process while reducing costs through virtual prototyping. DFSS methodologies typically start by defining a project and then analyzing customer needs—producing a set of customer critical to quality (CTQ) specifications. Incorporating a model-driven development process into the DFSS methodology can help ensure that these CTQs are met in the final product.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- ASIC vendors heed call for virtual prototyping tools
- Why you need RTL virtual prototyping
- Silicon virtual prototyping eyed for FPGAs
- A SystemC based Virtual Prototyping Methodology for Embedded Systems
Latest Articles
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety