RTL Prototyping Brings Hardware Speeds to Functional Verification

by Brian Caslis

From data-pattern dependencies to hardware/software integration issues, verifying a communication design's function and performance requires many execution cycles. RTL prototyping provides a way to get those cycles done in a short period of time relatively early in the design flow. As a result, this prototyping method offers excellent verification coverage before committing an ASIC design to silicon and brings a great deal of flexibility to complex system verification.

Of particular interest to designers of communications systems is the ability to verify hardware/software interactions before fabricating ASICs. If you are trying to be first to market with a product that supports a new communications standard, for example, you may have to deal with late changes as the committee finalizes the standard. A common way to compensate for the unpredictability of these changes is to make tradeoffs between hardware and software. While these tradeoffs allow for late design changes, they demand that you verify the performance and functionality of both the hardware and software - a difficult task unless you can test the design at or near real-time speeds.

RTL prototyping delivers those speeds by implementing ASIC logic in FPGAs and combining that functionality with off-the-shelf chips such as processors and PHYs. This article describes the RTL prototyping methodology and contrasts it with techniques such as simulation and emulation. This article also shows how design tools from both third party EDA vendors and FPGA vendors have greatly simplified the development of RTL prototypes. Communication systems designers who must maximize performance and minimize time to market will find such prototypes essential.