Using vector processing for HD video scaling, de-interlacing, and image customization
By Rumman Syed, On Demand Microelectronics
Mar 3 2006 (2:15 AM), Video/Imaging DesignLine
Image processing is a challenging discipline: high processing power is required to calculate image adjustments in real-time. Since the standards by which a qualitative picture is measured by are relative, experts have to face a serious debate, as defining the quality of an image still lies in the eye of the beholder.
Pictor image processing aims at providing adjustable high-quality images. The programmable features of Pictor mean a major step forward compared to other non-programmable image processing solutions which are currently offered on the market.
Maximum output through parallelism
Pictor is designed for real time image processing. It supports HD resolutions including 1080i. The core of the programmable platform is the VSP. The VSP, explained in detail in the next section, is made for digital signal processing applications and has high processing power and an equivalently high data bandwidth with low power usage. The image processor has a VLIW fixed-point arithmetic architecture and consists of parallel processing units (slices). Pictor has -- in comparison to the Video VSP used in the Scaleable Video Engine (SVEN) -- slices with separate quad data paths. The architecture of Pictor can, therefore, achieve a processing power of approximately 176 in complex giga-operations at only 230 MHz.
In addition, Pictor comes with special instructions including: SAD (SUM of Absolute Difference) and minimum-maximum search, which supports calculations in only one clock cycle. All image-processing algorithms are software implemented without requiring an additional hardware accelerator.
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- AceleradorSNN: A Neuromorphic Cognitive System Integrating Spiking Neural Networks and Dynamic Image Signal Processing on FPGA
- CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST
- Video and image processing design using FPGAs
- Video and image processing design using FPGAs
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs