Using FPGAs to build a compact, low cost, and low power Ethernet-to-Network Processor bridge
By Ted Marena, Lattice Semiconductor
Jul 11 2007 (12:49 PM), Embedded.com
As carriers and cable providers begin rolling out triple-play and VoD services to their customers, OEMs are increasing their development efforts to roll out IP- (Internet Protocol) based systems, including PONs, CMTS, IP DSLAMs and other access and last-mile equipment. The common underlying physical layer for this is the ubiquitous Ethernet technology, now coupled with sophisticated QoS (Quality of Service) overlays.
Within this context, design engineers are devoting more design effort to connect their switched Ethernet backplanes to the system line cards and, specifically, to their Network Processors. System architects often select Ethernet Switches and Network Processors based on their individual features and rarely consider the challenge of interconnecting the two.
Design engineers are then left with the challenge of developing the bridge, fitting the solution and implementing it cost effectively. Moreover, because both interfaces run at very high speeds, power is also a significant concern. All of these challenges are addressed in this article.
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power
- BCD Technology: A Unified Approach to Analog, Digital, and Power Design
- Build low power video SoCs with programmable multi-core video processor IP
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace