Using a "DSP-free" design for VOIP-enabled end-points
While ever-increasing volume demands help to drive some economies of scale, OEMs and ODMs are also looking to minimize product costs without sacrificing features or call quality.
VoIP end-points have been traditionally designed using a “tandem processor” architecture, which includes both a general-purpose applications processor and a DSP (Figure 1). The DSP handles the packet voice processing (voice encode/decode, tone generation and detection, echo cancellation, noise reduction, etc.), while the applications processor manages the VoIP call control protocol and user interface. This architecture has a number of drawbacks when attempting to address the design requirements of high-volume, low-cost VoIP end-points. For example: the need for both an applications processor and a DSP adds cost to the overall product; two discrete devices have a larger footprint than a single device; and the tandem processor architecture increases the overall power consumption.
Click here to read more ....
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors
- Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes
- A Resource-Driven Approach for Implementing CNNs on FPGAs Using Adaptive IPs
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
Latest Articles
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety