Timing closure in multi-level partitioned SoCs
Syed Shakir Iqbal , Mitul Soni & Gourav Kapoor (Freescale)
EDN (October 07, 2015)
With rising SoC design complexity, hierarchical backend design closure has become almost ubiquitous across the industry. Block and sub-block partitioning allow designers to exploit engineering and tool bandwidth more efficiently through optimized resource use. In addition, this approach is compatible with a bottom-to-top design approach.
This is in keeping with design practice wherein mature IP partitions are taken into the backend cycle while work is going on to finish the rest of the chip. Benefits like design-cycle reduction have prompted designers to push for multi-level partitioning schemes. However, as the level of hierarchical partitions increases, so do the challenges involved in their closure and signoff.
In this paper, we discuss the major timing and implementation challenges involved in multi-level hierarchical partitioning and modeling schemes.
To read the full article, click here
Related Semiconductor IP
- Ultra Ethernet MAC & PCS 100G/200G/400G/800G
- Ethernet PCS 100G/200G/400G/800G/1.6T
- Ethernet MAC 100G/200G/400G/800G/1.6T
- Junction Over-Temperature Detector with Linear Centigrade-to-Voltage Output - X-FAB XT018
- Performance P570 Gen 3
Related Articles
- FPGA prototyping of complex SoCs: Partitioning and Timing Closure Challenges with Solutions
- Complex SoCs: Early Use of Physical Design Info Shortens Timing Closure
- Timing Closure on FPGAs
- Latches and timing closure: a mixed bag
Latest Articles
- Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors
- TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
- Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
- A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
- ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits