Shift Left for More Efficient Block Design and Chip Integration

By David Abercrombie, Siemens EDA
EETimes (June 10, 2024)

Block/chip integration is a lot more complicated than it gets credit for. On the face of it, chip integration just involves collecting all the IP and other parts, then gluing them all together. In reality, chip integration is an overlapping series of iterations where the pieces that will make up the chip are still being designed, often by multiple different teams. The chip designer is trying to build something that is dependent on those components, but can’t wait until all the components are done to start the integration because of time-to-market pressures. That means that the chip designer is doing a lot of iterations with snapshots of IP blocks that are in various states of readiness. When they go through the flow, incomplete blocks will have millions of violations, too many to efficiently review taking a lot of time to debug and fix. How can block/chip integration flows change to be more efficient?

What if some of the time-consuming signoff verification tasks could be done quicker and earlier in the design process? Fix DRC errors with signoff accuracy directly from the place and route tool? Configure and manage all the verification jobs like a world-class maestro?

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