Reducing chip IR drop in backward-compatible power bar-limited LQFP SoCs
Shahab Akhtar , piyush mishra & AZEEM HASAN (Freescale)
EDN (June 22, 2015)
SoC design comes with its own set of complications and challenges. One of the biggest challenges that arises is backwards-compatible power bar-limited design in an LQFP package. As technologies are scaling, it is becoming more difficult to design the power grid for high frequency SoCs with limited power/ground lead availability on the LQFP package. In deep sub-micron designs, IR drop, least resistance path (LRP), and thermal profile can often significantly impact the functionality. In this paper, a new method is introduced which results in an optimized power grid structure.
Basics of backward-compatible & power bar-limited LQFP based SoCs
Backward compatible packages are a requirement of customers to save board cost and time so that they can expedite their products to market. In backward compatible design customer can easily move from single core designs to multiple core designs without changing its hardware as on LQFP package leads pin assignment is not changed. If we go for pin order change in the design which will add cost of new board & BOM to the customer & also product will delayed in the market. LQFP based design has been widely used because of its low cost product profile. If we are targeting low cost then we must choose backward compatible design when using LQFP packages in the products.
To read the full article, click here
Related Semiconductor IP
- 100-10Gbps Ethernet MAC Controller
- SD Card Controller
- AXI4 Memory Controller IP Core
- AXI-Lite I2C Controller Core
- LVDS Transceiver IP core
Related Articles
- Buffer design for reducing Hold violations & IR drop
- The pivotal role power management IP plays in chip design
- Reducing Time To Market for System On Chip Using IP Development and Integration Flow
- Novel and efficient power grid design for lesser metal layer process SOC's
Latest Articles
- LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation
- Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors
- Cryogenic Recharacterization of a Commercial 22 nm FD-SOI Foundry Standard-Cell Library
- A 105 MS/s 4.18 nJ/inference 0.765 mm² Mixed-Signal Streaming ML Engine for Wireless Baseband in 12LP+ FinFET
- Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains