Programmable logic carves further into the ASIC's territory
The key issues surrounding programmable logic never seem to change. If your quantity is going to be less than X, design your circuit with programmable logic. If you need more than X, go with an ASIC. Over the last few years, X has been increasing. Not too long ago, X was measured in the thousands (as in 100,000). Today, there are examples where programmable logic devices are employed into the millions.
The reasons for X (and the moving X), have to do with the per-unit cost of the programmable logic ICs versus the NREs associated with ASICs. While the NREs are on the rise, the programmable chips are coming down, fairly significantly.
According to one industry insider, in the United States, about one-third of all ASICs ship less than 50,000 devices over their lifetime. Around 47% ship 100,000 over their lifetime. If you look at NREs today, certainly for the latest process technologies, you could be looking at $500,000 for an ASIC spin. And not too many design teams get it done right on the first spin.
When you add the amortized NRE to the cost of the ASIC, the programmable part becomes pretty attractive. The programmable-logic industry is nearing the point where it can offer solutions for under $20 that basically make ASICs not viable for anything other than quantities in the millions. Add that to the fact the programmable part can get you to market faster.
Read more ....
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- Embedded Systems: Programmable Logic -> Focus is on the best ASIC design flow
- Amba bus may move MIPS into ARM territory
- Embedded Systems: Programmable Logic -> Programming enters designer's core
- Embedded Systems: Programmable Logic -> Common gateway networks enable remote programs
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace