Memory Admission and Result-Retention Sizing in an RV32IMC FPGA Soft Processor

By Yihang Dai, Shuyu Xu, Yinfeng Zhou, Chenglei Peng
Nanjing University, China

Abstract

In FPGA soft processors with shared backing block RAM, memory admission can stall a multiplication after its product has been prepared. We study how admission timing changes result retention in PaceRV, our board-tested five-stage RV32IMC core, using fixed binaries and matched dynamic instructions. Offering data requests one edge earlier reduces geometric-mean Embench cycles by 18.2% and retention opportunities from 375,063 to 4,373. Admission and retention cycle gains are conditional and non-additive. Under slower reads, a 99% capture target selects an 18-edge validity window with registered requests and 28 edges with early requests, although no multiplication matched within both measurement intervals waits longer. A predeclared sizing rule predicts opportunity recovery exactly in all finite tests, including kernels excluded from model development. Independent timing analysis closely estimates execution-cycle savings. The results support choosing admission first, then deciding whether to extend validity and sizing it against an explicit capture or missed-opportunity objective.

Index Terms — RISC-V, FPGA soft processor, memory admission, prepared arithmetic, performance prediction, result retention

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