System Verilog configurable coverage model in an OVM setup - concept of reusability

Parag Goel & Sakshi Bajaj, Applied Micro Circuits Corp.
EETimes (8/23/2010 4:30 AM EDT)

With the advent of a new era in verification technology based on an advanced HVL like System Verilog, the concept of random stimulus based verification was born, to verify today’s multi‐million gate designs. In concept, every verification engineer fancies the idea of random stimuli driven verification, but as is rightly said – “Everything comes with a cost” and the cost here is a big concern that haunts the life of every verification engineer:

• How do I close my verification?
• When can I say I am done?

To answer such questions, System Verilog as a language came up with the concept of functional coverage that is much more accurate of a measure compared to the traditional code coverage techniques. We concentrate mainly on this SV feature in our write‐up, adding one more dimension to it - configurability.

Methodology like OVM has brought in the concept of reusability of environment/agent (mainly consisting of driver/monitor/sequencer) across projects. But, on the other hand, a user tends to create a coverage model that is usually coupled very tightly to the specifications of the given project. In the process, he/she ends up writing a separate coverage model for every project, compromising the reusability aspect and violating the Methodology mantra! Keeping above limitation in view, we would like to present the user with one possible solution – configurable and reusable coverage model, sighting AMBA AXI protocol as the case study for discussion.

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