Software and hardware challenges due to the dynamic raw NAND market
Daniel Allred and Gaurav Agarwal, Texas Instruments
6/12/2011 7:27 PM EDT
NAND flash is the dominant type of non-volatile memory technology used today. Developers commonly face difficulties developing and maintaining firmware, middleware and hardware IP for interfacing with raw NAND devices. After reviewing the history and differentiated features of various memory devices, we’ll take a detailed look at common obstacles to NAND device development and maintenance, particularly for embedded and system-on-chip (SoC) developers, and provide some recommendations for handling these challenges.
To read the full article, click here
Related Semiconductor IP
- ONFI NAND PHY
- ONFI Nand Flash Software Driver
- ONFI 3.2 NAND Flash PHY IP Compliant to JEDEC
- ONFI 3.2 NAND Flash Controller IP Compliant to JEDEC
- ONFI 2 NAND Flash Controller IP Compliant to JEDEC
Related Articles
- Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon
- NOR continues to battle NAND flash memory in the handset
Latest Articles
- SCENIC: Stream Computation-Enhanced SmartNIC
- Agentic AI-based Coverage Closure for Formal Verification
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities