Maximizing performance in FPGA systems
Adrian Cosoroaba, Virtex solutions manager at Xilinx Inc.
(01/02/2006 10:00 AM EST)
EE Times
With programmable hard intellectual property like DSP building blocks, serdes and embedded processors, FPGAs have become complex systems-on-chip. As a result, extracting higher performance involves far more than just cranking up the fabric clock rate. Typically, one must balance a complex set of requirements-I/O bandwidth, hardware logic and/or embedded-processing performance.
Harnessing built-in FPGA features for maximum performance also takes the right combination of design techniques. Tool settings are needed that optimally implement the functional description as written in RTL code. Each phase of design development, synthesis and implementation is critical.
System architecture must be considered for effective trade-offs between programmable hardware resources. With the architecture defined and RTL code ready, synthesis tools assign the design's basic conceptual building blocks to technology cells.
(01/02/2006 10:00 AM EST)
EE Times
With programmable hard intellectual property like DSP building blocks, serdes and embedded processors, FPGAs have become complex systems-on-chip. As a result, extracting higher performance involves far more than just cranking up the fabric clock rate. Typically, one must balance a complex set of requirements-I/O bandwidth, hardware logic and/or embedded-processing performance.
Harnessing built-in FPGA features for maximum performance also takes the right combination of design techniques. Tool settings are needed that optimally implement the functional description as written in RTL code. Each phase of design development, synthesis and implementation is critical.
System architecture must be considered for effective trade-offs between programmable hardware resources. With the architecture defined and RTL code ready, synthesis tools assign the design's basic conceptual building blocks to technology cells.
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