Mapping custom instructions for the Toshiba media embedded processor (MeP)

By Hammad Hamid, Celoxica,
Courtesy of Programmable Logic DesignLine
Dec 21 2005 (11:40 AM)

Although processor to hardware partitioning can be successfully resolved by a combination of designer experience, precedent, tools, such as profilers and data-transfer analyzers …and a degree of patience and understanding, no engineer underestimates this task. Toshiba's MeP (media embedded processor) is a case in point.

Developed by Toshiba, the MeP is a programmable platform for creating a system-on-chip (SoC) that is targeted at applications that require digital media processing functionality such as video and audio. The multiple standards that apply to digital media are constantly evolving; thus, in order to be competitive in this dynamic environment, complicated functions need to be implemented in a short space of time and in a platform that can efficiently reuse intellectual property (IP). As an answer to this, the MeP is provided to users as soft IP. The MeP IP is divided into the following categories:

• Core IP: The processor core section that is central to MeP.

• Extension unit IP that realizes high-performance and sophisticated MeP modules by being connected to extension interfaces of the MeP core.

• Peripheral IP, such as the DMA controller and bus interfaces that form a MeP module or MeP SoC.

Once the partitioning is has been completed and verified as being accurate, the next challenge is to map the partitioned design onto a processor and custom hardware architecture that consists of fixed buses. In a scenario based on designing with the MeP in its Developers Kit, the custom hardware design is wrapped with logic compatible to the chosen bus. The kit provides three main types of bus: the control bus, the DSP Instruction bus, and the local bus. These buses are very different in their protocols, and user mapped logic is subsequently affected when mapping across them. The size, depth, and flow of logic mapped onto these buses will affect the performance of the entire system during transactions.

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