It's Beginning to Look A Lot Like ASIC - Tools Mirror the Evolution of Programmable SOC Complexity

by Jerry Ascierto

The line between ASICs and PLDs is beginning to blur.

Smaller process geometries, architectural advancements, and ever-expanding gate counts have given PLD vendors the ability to offer SOC designs that rival standard cell ASICs.

More and more fixed functionality is being integrated into PLDs, with on-board CPUs, SRAM, DSPs, high speed I/O, and a host of complex IP upping the performance ante. Xilinx Inc. and Altera Corp. continue to battle it out on this front in hopes of wresting market share away from the standard cell ASIC market.

Networking and telecomm applications are driving this wave of emerging architectures, where programmability offers flexibility in the face of standards work still under development. But this growing degree of PLD functionality is enabling new applications in such markets as consumer electronics (PDAs), aerospace, industrial computers and automotive.

Though still in its infancy, the programmable system on a chip approach-similarly dubbed the SOPC (System on a Programmable Chip) by Altera, and the FPSOC (Field Programmable System on a Chip) by Xilinx-is beginning to emerge as a cost-effective solution to low and mid-range ASIC designs.

As more functionality is embedded on chip-and as ASIC vendors concurrently begin to embed PLD blocks into an ASIC-the distinction between the two architectures begins to blur.

"An embedded processor is just the beginning of this. We're putting more and more dedicated silicon into FPGAs," said Lee Hansen, a product marketing manager at Xilinx (San Jose). "The other side of the equation is there's room for putting more programmable logic on ASICs as well."