Is the cost reduction associated with IC scaling over?
Zvi Or-Bach, MonolithIC 3D Inc.
EETimes (7/16/2012 12:20 PM EDT)
The last 50 years of the semiconductor industry have been all about the manifestation of Moore's Law with regard to the dimensional scaling of Integrated Circuits (ICs). As consumers of electronic devices, we all love to see better products at a lower cost with each and every new product cycle. But now storm clouds are forming, as was recently publicly expressed in the article Nvidia deeply unhappy with TSMC, claims 20nm essentially worthless.
Clearly, dimensional scaling is no longer associated with lower average cost per transistor. The chart below, published by IBS about a year ago, shows the diminishing benefit of cost reduction from dimensional scaling. In fact, the chart indicates that the 20nm node might be associated with higher cost than the previous node.
To read the full article, click here
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related Articles
- Cost Reduction and Improved TTR with Shared Scan-in DFT CODEC
- Extending 8K over a single, cost-effective wire with TICO lightweight compression
- Multiplexed Energy Metering AFEs Ease ASIC Integration and Provide Significant Cost Reduction
- Survey shows SoC design data management is mission critical
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs