Integrating 'hard' IP into a system-on-chip
Craig Zajac and Troy Gilliland
(10/16/2006 9:00 AM EDT)
The integration of "hard" intellectual property blocks--those delivered as GDSII databases--lets system designers focus on their core competency by outsourcing certain blocks that previously had to be developed internally. Consequently, purchasing and integrating hard IP blocks is becoming a way of life for SoC designers. Off-the-shelf IP blocks are available for almost every function--from A/D converters to ZigBee transceivers.
Selecting a quality IP supplier is a top concern in yielding a successful IP integration. To that end, the Virtual Socket Interface Alliance and the Fabless Semiconductor Association are working with companies to develop a standard, objective quality metric for hard IP blocks and their suppliers.
During the course of delivering such IP over the past several years, Impinj has witnessed a range of IP integration experiences, from the painless to the nearly disastrous. Most of the pitfalls can be avoided by following a few recommendations.
(10/16/2006 9:00 AM EDT)
The integration of "hard" intellectual property blocks--those delivered as GDSII databases--lets system designers focus on their core competency by outsourcing certain blocks that previously had to be developed internally. Consequently, purchasing and integrating hard IP blocks is becoming a way of life for SoC designers. Off-the-shelf IP blocks are available for almost every function--from A/D converters to ZigBee transceivers.
Selecting a quality IP supplier is a top concern in yielding a successful IP integration. To that end, the Virtual Socket Interface Alliance and the Fabless Semiconductor Association are working with companies to develop a standard, objective quality metric for hard IP blocks and their suppliers.
During the course of delivering such IP over the past several years, Impinj has witnessed a range of IP integration experiences, from the painless to the nearly disastrous. Most of the pitfalls can be avoided by following a few recommendations.
To read the full article, click here
Related Semiconductor IP
- Secure Boot Loader
- Memory Subsystem
- 4/8-bit mixed-precision NPU IP
- Compiler-centric single-core LPU
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
Related Articles
- AceleradorSNN: A Neuromorphic Cognitive System Integrating Spiking Neural Networks and Dynamic Image Signal Processing on FPGA
- CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus
- A 24 Processors System on Chip FPGA Design with Network on Chip
- Using non-volatile memory IP in system on chip designs
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection