SoCs can hold key to system security
By Albert Chiang, MIPS Technologies Inc.
EE Times (04/02/07, 09:00:00 AM EDT)
A system is only as secure as its weakest link, and security becomes ever more important as more equipment moves to a system-on-chip approach. Here we look at the security options available to SoC designers.
SoC designers are increasingly aware of the need for security, in addition to performance, in consumer devices to protect both the device and its content from tampering and copying.
Designing a secure system requires a chipwide approach; retrofitting a system with security functions is only a temporary fix. Protecting a device's secret key and content as well as understanding the basic requirements of a secure SoC are vital to a system designer's ability to create leading-edge products.
With more e-commerce applications running on phone handsets today, mobile systems are now addressing security concerns. While mobile processors previously relied on subscriber identity module cards as the secure element, processor and integration architectures are now essential to the security of the whole system, as more peripherals are integrated into a single chip.
Three elements are vital to a secure system: secure peripherals that prevent unauthorized access, ideally with multiple levels of access; a trusted environment to run trusted software and securely store sensitive data; and cryptographic acceleration.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- Secure SOC for Security Aware Applications
- Building security into an AI SoC using CPU features with extensions
- Add Security And Supply Chain Trust To Your ASIC Or SoC With eFPGAs
- A Survey on SoC Security Verification Methods at the Pre-silicon Stage
Latest Articles
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety