Improving reliability of non-volatile memory systems
Daisuke Nakata, Cypress
embedded.com (November 19, 2018)
Complex systems like Advanced Driver-Assistance Systems (ADAS), medical, and industrial applications need to be reliable, secure, and safe. In these systems, firmware and associated data are stored in Non-Volatile Memory (NVM) because code and data must be retained when power is not being supplied. Thus, NVM plays a crucial role in system reliability.
NVM reliability can be expressed in two ways: data retention time and cycling endurance. Retention time dictates how long NVM can hold data and code reliability. Endurance measures how many times the NVM can be rewritten and still reliably hold data and code. To offset these limitations, designers often employ special host software and/or hardware such as a Flash File System that employs wear-leveling and/or error code correction (ECC) technology to ensure data has not changed since it was last written. These measures result in system overhead, often negatively impacting performance. In addition, complex remedies reduce system robustness, especially in cases of NVM operation during a power failure.
Today’s NVM memory employs next-generation technology to increase NVM reliability. Companies like Cypress, with its Semper NOR Flash Memory, have introduce advanced measures such as on-die ECC and internal wear leveling to substantially improve retention and endurance in Flash NVM (see Figure 1).
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- Universal NVM Express Controller (UNEX)
- NVM MTP EEPROM TSMC 65nm LP 2.5V SVT, SVT/HVT
- NVM MTP EEPROM TSMC 40nm LP 2.5V
- NVM MTP EEPROM TSMC 180nm BCDG2 5V
Related Articles
- The benefit of non-volatile memory (NVM) for edge AI
- Selecting the right Nonvolatile Memory IP: Applications and Alternatives
- NAND Flash memory in embedded systems
- Argument for anti-fuse non-volatile memory in 28nm high-K metal gate
Latest Articles
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices