The benefit of non-volatile memory (NVM) for edge AI
Eran Briman, Weebit Nano
embedded.com (September 15, 2023)
In low-power IoT and edge AI applications, AI models can be small enough to fit into the internal NVM of an SoC. The on-chip NVM could be used for both code storage and to hold the AI weights and CPU firmware.
Ongoing innovation in semiconductor technologies, algorithms and data science are making it possible to incorporate some degree of AI inferencing capability in an increasing number of edge devices. Today we see it in computer vision applications like object recognition, facial recognition, and image classification on products from phones and laptops to security cameras. In industrial systems, inferencing enables predictive equipment maintenance and lets robots perform tasks independently. For IoT and smart home products, AI inference makes it possible to monitor and respond in real time to various sensor inputs.
The lowest cost processing solutions that support AI inferencing today are off-the-shelf single-chip microcontrollers used for IoT systems. Such chips combine a general-purpose CPU, SRAM and IO functions with non-volatile memory (NVM). However, these chips implement the AI algorithms in software running on the CPU which can deliver only modest performance and are only practical for basic inference. Scaling a single-chip solution to provide higher performance inference presents a challenge to designers.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- RERAM Memory Model
- ReRAM NVM in SkyWater 130nm
- ReRAM Secure Keys
- ReRAM as FTP/OTP Memory
Related Articles
- MIPI in next generation of AI IoT devices at the edge
- The Growing Importance of AI Inference and the Implications for Memory Technology
- Revolutionizing Consumer Electronics with the power of AI Integration
- Parsing the Mindboggling Cost of Ownership of Generative AI
Latest Articles
- ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs
- ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training
- OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
- CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
- CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST