Selecting the right Nonvolatile Memory IP: Applications and Alternatives
By Craig Zajac, Virage Logic
Embedded.com (05/24/10, 06:45:00 PM EDT)
New applications and use models are showing up every day for embedded nonvolatile memory and just as rapidly, new technologies and offerings are becoming available to service those needs. With the breadth of solutions available in the market today, it can become overwhelming for system designers to identify which option is best suited for their given needs.
Application Space Overview. Before starting down the path of evaluating the various options, it is critical to understand real requirements and use model of nonvolatile memory in the system. The two primary features of embedded nonvolatile memory are bit count and endurance cycles.
The endurance cycle specification defines the number of times the memory can be written / re-written. Bit count, also specified in bytes, is simply the amount of data that can be stored in a given block.
Other parameters such as supply voltage, power consumption, etc. are critical to some applications, but are generally secondary to bit count and endurance when looking at the entire landscape.
To read the full article, click here
Related Semiconductor IP
- Multiple - Time Programmable Non-Volatile Memory
- Expanded Serial Peripheral Interface (xSPI) Slave Controller
- Expanded Serial Peripheral Interface (xSPI)Master Controller
- XSPI Master IIP
- XSPI Controller IIP
Related Articles
- Argument for anti-fuse non-volatile memory in 28nm high-K metal gate
- Resistive RAM for next-generation nonvolatile memory
- Using non-volatile memory IP in system on chip designs
- Data storage in non-volatile memory
Latest Articles
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices