How to design a better 1.5-V 2.4-GHz CMOS PLL for wireless applications
Mingliang Liu, Lava Technologies
Feb 21, 2006 (2:05 PM), CommsDesign
Since the VCO is one of the most important elements in the PLL system it is an appropriate place to begin this article, which addresses the challenges of designing a 1.5-V 2.4-GHz CMOS Phase Locked Loop (PLL) for wireless LAN applications. The design assumes a specific process, namely TSMC 0.35 micron technology.
The schematic of the VCO is shown in Figure 1. Transistors M8 and M9 form a NMOS cross-coupled differential pair to provide the negative resistance, which is required for generating an oscillation. M0, M1 and R3 form the biasing network for the oscillator. L7 and C8 form the filtering network to suppress the high frequency noise generated by the bias current source.
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