Building high-speed FPGA memory interfaces
By Paul Evans, Altera Corp.
pldesignline.com (September 02, 2009)
Building reliable, high-speed memory interfaces target FPGA I/O structures as well as intellectual property (IP) used within design software to allow rapid configuration of memory interfaces. These techniques use IP to help gain an extra timing margin at high speed operation
External double data rate (DDR) memory types are a common part of many FPGA designs. This article will examine the architecture behind the I/O blocks in high-end FPGAs (i.e. Altera's Stratix IV devices) and how these FPGAs are able to achieve 533 MHz or 1067 Mbps data rates. It also examines the tools that are used to build a memory interface, and provide a brief overview of the timing budget.
These FPGAs support the five leading double data rate memory types, that is DDR1, DDR2, and DDR3 as well as QDRII+ and RLDRAM as well as other memory interface types. RLDRAM is supported at rates of up to 1,600 megabits per second or 400 megahertz, QDRII+ at 1,400 megabits per second, and DDR3 at speeds of up to 533 megahertz or 1,067 megabits per second.
pldesignline.com (September 02, 2009)
Building reliable, high-speed memory interfaces target FPGA I/O structures as well as intellectual property (IP) used within design software to allow rapid configuration of memory interfaces. These techniques use IP to help gain an extra timing margin at high speed operation
External double data rate (DDR) memory types are a common part of many FPGA designs. This article will examine the architecture behind the I/O blocks in high-end FPGAs (i.e. Altera's Stratix IV devices) and how these FPGAs are able to achieve 533 MHz or 1067 Mbps data rates. It also examines the tools that are used to build a memory interface, and provide a brief overview of the timing budget.
These FPGAs support the five leading double data rate memory types, that is DDR1, DDR2, and DDR3 as well as QDRII+ and RLDRAM as well as other memory interface types. RLDRAM is supported at rates of up to 1,600 megabits per second or 400 megahertz, QDRII+ at 1,400 megabits per second, and DDR3 at speeds of up to 533 megahertz or 1,067 megabits per second.
To read the full article, click here
Related Semiconductor IP
- Mesochronous Bridge for PCIe/CXL
- AI-native GPU
- OpenGMSL Verification IP
- OpenGMSL Leaf IP
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
Related Articles
- High-Speed Serial fully digital interface between WLAN RF and BB chips
- DDR3 memory interface controller IP speeds data processing applications
- AMS and High-speed Interface IP Design Enablement in GLOBALFOUNDRIES 65LPe Process Technology
- Improve FPGA communications interface clock jitters with external PLLs
Latest Articles
- FlexSpIM: An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Hybrid Stationarity
- MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators
- Analog Pin Directionality as an Exfiltration Attack Surface in Mixed-Signal ICs
- SIMT-Aware Lockstep Verification and Functional-Coverage Closure Methodology for an Open-Source RISC-V GPGPU: A UVM 1.2 Environment
- Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing