H.264 encoder design using Application Engine Synthesis
By Craig Gleason , Synfora, Inc.
May 09, 2008 -- videsignline.com
System on Chip design is driven by complex consumer devices that rely on standard algorithms such as H.264, WiMax, or JPEG for their defining capabilities. These reference standards allow room for innovative implementation that result in differentiated products.
Designing these SoCs is an enormous undertaking, with significant cost and risk associated with each project. One way to reduce both project cost and schedule risk is to use Application Engine Synthesis (AES) for the automatic creation of an application engine such as an H.264 encoder from a sequential, untimed C algorithm.
The goal of the project described in this article was to emulate a typical design process for an H.264 encoder and to determine AES's ability to generate efficient hardware designs for real-life, high-complexity applications, while also demonstrating significant savings in terms of time and cost (of resources). We set the target of building an H.264 encoder for D1 size video that would meet real-time requirements (30 frames per second) on the most stringent test sequences, and aimed to complete the project in less than 5 months.
This article describes the process used, targets met, and productivity gains achieved.
May 09, 2008 -- videsignline.com
System on Chip design is driven by complex consumer devices that rely on standard algorithms such as H.264, WiMax, or JPEG for their defining capabilities. These reference standards allow room for innovative implementation that result in differentiated products.
Designing these SoCs is an enormous undertaking, with significant cost and risk associated with each project. One way to reduce both project cost and schedule risk is to use Application Engine Synthesis (AES) for the automatic creation of an application engine such as an H.264 encoder from a sequential, untimed C algorithm.
The goal of the project described in this article was to emulate a typical design process for an H.264 encoder and to determine AES's ability to generate efficient hardware designs for real-life, high-complexity applications, while also demonstrating significant savings in terms of time and cost (of resources). We set the target of building an H.264 encoder for D1 size video that would meet real-time requirements (30 frames per second) on the most stringent test sequences, and aimed to complete the project in less than 5 months.
This article describes the process used, targets met, and productivity gains achieved.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- Time-Domain Analog Design: Why and How
- Why Hardware Root of Trust Needs Anti-Tampering Design
- How to manage changing IP in an evolving SoC design
- How to Elevate RRAM and MRAM Design Experience to the Next Level
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs