Going multicore presents challenges and opportunities

By Anant Agarwal and Markus Levy
Apr 10 2007 (0:30 AM), Embedded Systems Design

Although multicore technology offers a game-changing opportunity for improvements in processing performance and power efficiency, it also brings about many new design and programming challenges. As the processor industry moves forward, the "three Ps," power efficiency, performance, and programmability, are the yardstick by which various architectures will be judged. Interestingly, power efficiency and performance are not only the biggest opportunities afforded by multicore technology but also the most significant challenges as we scale the number of cores beyond today's single-digit designs. Another daunting challenge involves the programming model required for efficient use of multiple cores on a chip. Here's where organizations, such as the Multicore Association, will help alleviate some of these challenges.

Application demand for computing cycles in virtually every domain, from the embedded systems market to the desktop PC, continues to increase unabatedly. Modern video workloads, for example, require 10 to 100 times more compute power than that of a few years ago due to increasing resolutions (from standard definition to HD), more sophisticated compression algorithms (MPEG2 to H.264), and greater numbers of channels.

Unfortunately, the delivered performance of conventional, sequential processors, and digital signal processors hasn't kept pace with this demand. Reasons for this widening gap include diminishing returns from single-processor mechanisms such as caching and pipelining, wire delays, and power envelopes. Similarly, custom silicon is too expensive to build and FPGAs are too difficult to program.

Along with the wide range of application domains that do (or will) use multicore technologies, comes a wide range of definitions and implementations of multicore. In fact, there are so many definitions and implementations that it suffices to say that multicore refers to a single chip containing multiple visibly distinct processing engines, each with independent control (or program counters). In a sense, this can be viewed as a multiple-instruction-multiple-data (MIMD) style of computation. But even simplified as this definition is, multicore implementations can take many different forms; Figure 1 provides just a few examples.

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