Getting started in structured assembly in complex SoC designs
By Tim Schneider, Arteris IP (July 27, 2022) - EDN
The integration level of a system-on-chip (SoC) is defined in RTL, just like the rest of the design. Historically, RTL has been built through text editors. However, a decade or more ago, the sheer complexity of that task for the largest SoCs became unmanageable; now, most SoCs cross that threshold. Why is this? The number of IPs in the SoC is certainly a factor, and the number of connections explodes at the integration level. For example, a single AXI channel connection can have 25 signals. Next, AMBA to AMBA connections in multiple flavors proliferate across designs.
Also, designers must include the integration infrastructure—clocks, resets, power management and test—which must evolve as the design progresses. These requirements can add up to 10,000 connections in an unexceptional SoC. Connections between IPs may have hundreds of ports with multiple configuration tie-off options. These ports may be left open or connected and have many other significant considerations. Typical interconnect complexity is evident even in a small subset of the design.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- Optimizing Communication and Data Sharing in Multi-Core SoC Designs
- Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs
- Understanding LTTPR: Enabling High-Speed DisplayPort Interconnects in Complex System Designs
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace