FPGA partial reconfiguration mitigates variability
Eric Shiflet and Lee Hansen, Xilinx
(04/03/2006 9:00 AM EDT), EE Times
Design variability is rapidly becoming the “norm” for electronics products. From packaging to logic functionality, electronic end products are expected to be more customized and configurable based on customer demand and field environment.
For logic design, this means the hardware must be able to handle a variety of functions, which leads to more devices and more real estate. A common method to handle this additional functionality has been to move them into switchable software modules handled by a microprocessor. However, a growing number of applications are relying on FPGA-based partial reconfiguration technology to leave logic functions in hardware, switch them in and out on demand — all while leaving your core logic running.
(04/03/2006 9:00 AM EDT), EE Times
Design variability is rapidly becoming the “norm” for electronics products. From packaging to logic functionality, electronic end products are expected to be more customized and configurable based on customer demand and field environment.
For logic design, this means the hardware must be able to handle a variety of functions, which leads to more devices and more real estate. A common method to handle this additional functionality has been to move them into switchable software modules handled by a microprocessor. However, a growing number of applications are relying on FPGA-based partial reconfiguration technology to leave logic functions in hardware, switch them in and out on demand — all while leaving your core logic running.
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Articles
- Partial reconfiguration in FPGA rapid prototyping tools
- An MDE Approach For Implementing Partial Dynamic Reconfiguration In FPGAs
- Accelerate partial reconfiguration with a 100% hardware solution
- FPGA design from scratch
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow