A next-gen FPGA-based SoC verification platform
Howard Mao, SpringSoft
EETimes (11/1/2010 1:40 PM EDT)
System-on-Chip (SoC) designs continue to increase in size and complexity. At the same time, market windows are shrinking and today's electronic markets are extremely sensitive to time-to-market pressures. All of this is putting tremendous demands on SoC design and verification teams. Indeed, it is now widely accepted that verification accounts for around 70 percent of the total SoC development cycle. Thus, anything that decreases verification costs, speeds verification runs, and allows verification to be deployed earlier in the development cycle is of extreme interest.
This article begins with an introduction to the major elements that comprise a typical SoC design and verification environment. Also considered are the advantages and disadvantages of conventional verification solutions, including software simulation, hardware-assisted acceleration and emulation, and the use of FPGA-based prototype boards. The article goes on to describe an innovative and affordable way in which standard FPGA-based prototype boards are turned into full-blown desktop emulators. This proposed approach enables a paradigm shift that could dramatically increase the verification efficiency of off-the-shelf and custom-designed FPGA-based prototype boards by automating their existing in-circuit emulation capabilities and adding new co-emulation and co-simulation capabilities.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- A configurable FPGA-based multi-channel high-definition Video Processing Platform
- Shifting Mindsets: Static Verification Transforms SoC Design at RT Level
- Efficient methodology for verification of Dynamic Frequency Scaling of clocks in SoC
- Verification of various SoC features through SV assertions
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM