Automotive Design Needs Efficient Verification to Survive
By Jean-Marie Brunet, Mentor Graphics
EETimes (July 28, 2020)
The business of building and selling vehicles is changing like never before in the history of the automobile. The quest for cars that drive themselves has completely upended what it means to design a car — and, indeed, what it means to own a car. Exactly how this will all settle out isn’t yet clear. What is clear is that automotive OEMs, and Tier 1 & Tier 2 suppliers are seeing challenges to their historical relationships as electronics pervade future vehicles.
Coupled with increased regulatory requirements for emissions, fuel efficiency, and safety, these electronics will need to be integrated more tightly with the volumes of software that will operate on them. That makes for changing alliances. Traditional and new participants will need to find ways to collaborate and innovate as their roles evolve. One common theme dominates for all players: the challenge of proving that all of these electronics and their software will run smoothly, correctly, efficiently, and safely.
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Articles
- Efficient methodology for verification of Dynamic Frequency Scaling of clocks in SoC
- An efficient way of loading data packets and checking data integrity of memories in SoC verification environment
- Efficient methodology for design and verification of Memory ECC error management logic in safety critical SoCs
- Safety Verification and Optimization of Automotive Ethernet Using Dedicated SoC FIT Rates
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow