Facilitating System-in-Package (SiP) design
Keith Felton (Cadence Design Systems) and Jamie Metcalfe (Optimal Corp)
(06/05/2006 4:46 PM EDT), EE Times
In the latest move in the cost, density, and time-to-market battles, a number of wireless and consumer-focused IC and systems companies are turning to System-in-Package (SiP) design to gain a competitive advantage. Hemmed in, on the one hand, by the technical challenges of producing compact, high-performance, multi-function products and, on the other, by a fast-moving, competitive marketplace, they are scrambling to reduce every cent in product cost and every hour spent in design.
To this end, SiP design offers clear advantages — more function in less space and reduced design cycle times. But to deliver on the promise of SiP design, EDA software providers have to develop tools with new functionality and present scalable design methods and flows.
An ideal solution will give SiP design team members the ability to create die abstracts in an IC environment, RF design in an IC and substrate design environment, and package/board co-design in an integrated packaging/PCB design environment.
(06/05/2006 4:46 PM EDT), EE Times
In the latest move in the cost, density, and time-to-market battles, a number of wireless and consumer-focused IC and systems companies are turning to System-in-Package (SiP) design to gain a competitive advantage. Hemmed in, on the one hand, by the technical challenges of producing compact, high-performance, multi-function products and, on the other, by a fast-moving, competitive marketplace, they are scrambling to reduce every cent in product cost and every hour spent in design.
To this end, SiP design offers clear advantages — more function in less space and reduced design cycle times. But to deliver on the promise of SiP design, EDA software providers have to develop tools with new functionality and present scalable design methods and flows.
An ideal solution will give SiP design team members the ability to create die abstracts in an IC environment, RF design in an IC and substrate design environment, and package/board co-design in an integrated packaging/PCB design environment.
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Articles
- Emerging Trends and Challenges in Embedded System Design
- How to manage changing IP in an evolving SoC design
- Functional Safety in Road Vehicles
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow