Facilitating at-speed test at RTL (Part 2)
Dr. Ralph Marlett, Kiran Vittal, Atrenta Inc.
4/20/2011 2:15 AM EDT
Part 1 of this series discusses the problems with at-speed testing, and the various defect models and manufacturing test techniques. This part will tackle at-speed timing closure rules and at-speed coverage. It also looks into the at-speed coverage estimation and diagnosis of SpyGlass-DFT DSM.
The SpyGlass-DFT DSM product provides timing closure analysis and RTL testability for deep subµm (DSM) defects associated with at-speed testing. It is touted to provide accurate RTL fault coverage estimation for transition delay testing, together with diagnostics for low fault coverage, early in the design flow.
Figure 1: Complete RTL analysis solution for stuck-at and at-speed testing.
To access the full Design Article by Atrenta Inc. (in PDF Format), click here.
Read also:
Facilitating at-speed test at RTL (Part 1)
About the authors:
. Dr. Ralph Marlett, Product Director, Atrenta Inc.
. Kiran Vittal, Product Marketing Director, Atrenta Inc.
Courtesy of EE Times India
Related Semiconductor IP
- Ultra Ethernet MAC & PCS 100G/200G/400G/800G
- Ethernet PCS 100G/200G/400G/800G/1.6T
- Ethernet MAC 100G/200G/400G/800G/1.6T
- Junction Over-Temperature Detector with Linear Centigrade-to-Voltage Output - X-FAB XT018
- Performance P570 Gen 3
Related Articles
- Facilitating at-speed test at RTL (Part 1)
- Moving DFT to RTL overcomes test vector issues
- Static Checks for Power Management at RTL
- Power analysis of clock gating at RTL
Latest Articles
- Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors
- TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
- Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
- A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
- ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits