Static Checks for Power Management at RTL

Is this a case of "a stitch in time saves nine?"

By Krishna Balachandran, Director, Synopsys, Inc.
EDA DesignLine -- (05/20/08, 08:34:00 AM EDT)

The advent of handheld devices signaled an era of battery conservation. The demanding need of the consumer market to drive down the price of the handhelds called for the integration of several functions into a single gadget, and multiple applications running on a single gadget have put tremendous pressure on battery life. Power management is no longer an afterthought, but a necessity if these gadgets are to have any meaningful life as a mobile device.

Power management implies extra design effort. Design techniques have concentrated on conserving energy by allowing high-speed parts of the design to operate at higher voltages and frequencies and segmenting low-speed blocks to operate at lower voltages and frequencies. Of course, what is created must be verified. Power management design is therefore associated with increased verification effort.

Verification teams must come up with the right strategy for verifying low power designs to have even a prayer to complete verification of the critical functions in different power modes and have any measure of confidence that the design will work in the field. The fierce nature of competition in the consumer industry doesn't allow any extra time to complete the verification task. In fact, if anything, product development cycles are shrinking. A well-known fact of product development is that a bug that escapes detection at RTL will cost a lot more to fix downstream in the design cycle. A bug that is found in silicon is extremely expensive from not just a cost point of view, but also in terms of missed market windows and lost opportunities.

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