Evaluating performance of memory technologies in networking applications
New memory technologies are continually being introduced to provide enhanced performance in applications such as graphics and network switching. This article provides an overview of the different mainstream and niche technologies in the market today, and identifies the parameters that determine the performance of these technologies in switching applications.
While the mainstream market, both PC and embedded applications is making the transition from SDRAM to Double Data Rate (DDR) SDRAM to ensure performance requirements are met, still greater bandwidth is needed for specific applications. In addition to RDRAM (Rambus™) memory technology, newer network RAM technologies such as Fast Cycle RAM (FCRAM™) and Reduced Latency DRAM (RLDRAM™) are working to fill the bandwidth gap by utilizing a redesigned DDR-based DRAM core. Other types of memory technologies such as high-speed SRAMs (static RAM) like QDR and SigmaRAM, and CAMs (Content Addressable Memory) can also meet the bandwidth and latency requirements, but can be more costly and have limited densities. The FCRAM and RLDRAM memory architectures have been optimized for faster access times while supporting the larger densities needs of network applications.
Read more ....
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- A Memory Subsystem Model for Evaluating Network-on-Chip Performance
- Memory Prefetching Evaluation of Scientific Applications on a Modern HPC Arm-Based Processor
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM