Effective Timing Strategies for Increasing PCIe Data Rates

Senad Lomigora, Application Engineering Manager, ON Semiconductor
EDN (July 28, 2015)

Introduction: PCIe, the High-Performance Interconnect

The advanced serial communication standard Peripheral Component Interconnect (PCI) was originally developed for use in personal computers, to overcome challenges such as clock and data-signal skew that limit the bandwidth of parallel bus standards. As a serial interconnect, PCI also helps avoid the high pin count needed to implement a parallel data link.

PCI was later enhanced to PCI Extended (PCI-X) and then to PCI Express (PCIe), which is a point-to-point full duplex serial computer expansion bus standard that replaces the earlier standards and allows a faster and more flexible solution.

PCIe has now evolved through three generations to satisfy demands for higher speed and data throughput. The first generation, PCIe 1.1, allowed effective data throughput of 500MB/s per lane using a raw data transfer rate of 2.5GT/s (Giga-Transfers per second) and 8b/10b data encoding. PCIe 2.1 increased the data throughput to 1GB/s per lane by raising the transfer rate to 5.0GT/s. PCIe 3.0 achieves data throughput of 2GB/s per lane by a combination of increasing the transfer rate further to 8GT/s and using the more efficient 128b /130b encoding scheme.

One PCIe lane contains two differential pairs comprising one transmit and one receive channel. The total PCIe link data bandwidth can be scaled by adding extra lanes. This flexibility has made PCIe popular in applications like servers, network attached storage, network switches, routers, and set-top boxes. The strict timing budgets and system challenges inherent in these applications place exacting demands on PCIe clock performance.

PCIe specifies a 100MHz external reference clock (Refclk), accurate to within ± 300ppm, for coordinating data transmission between two PCIe devices. The PCIe standards allow scope for three clock distribution methods. These are Common Clock, Data Clock and Separate Clock architectures. The same clock accuracy of ± 300ppm is required for all clocking methodologies.

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