EDA focus shifts to system level design
Walden Rhines, Mentor Graphics
2/16/2011 8:55 AM EST
Companies designing complex electronics always face numerous challenges, which keep evolving, because each problem solved enables new advances that in turn lead to new challenges. The year ahead will see increased system engineering content in chip- and board-level designs.
Problems that used to be solvable at the physical or register transfer level (RTL) are now being increasingly impacted by system architecture. Much of the challenge of low power design used to be limited to the physical implementation, but now the primary impact is at the system architecture level. As a result, system design trade-offs are becoming an increasingly important part of the job of the chip designer.
In 2011 and beyond, more and more of the design task will entail evaluating the chip architecture at the system level to optimize power and performance.
Previously, chip designers used to work independently from the embedded software developers. Now the development and verification of embedded software with hardware is the largest component of chip and system design.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- The Challenges and Benefits of Analog/Mixed-Signal and RF System Verification above the Transistor Level
- VMM based multi-layer framework for system level verification
- Metrix Driven Hardware Software System Level Verification
- Static Formal Verification for System Level Verification
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace