DSP options to accelerate your DSP+FPGA design
Suhel Dhanani, Altera Corporation
EETimes (10/14/2010 2:56 PM EDT)
Although signal processing is usually associated with digital signal processors, it is becoming increasingly evident that FPGAs are taking over as the platform of choice in the implementation of high-performance, high-precision signal processing.
For many such applications, the choice generally boils down to using either a single FPGA, a FPGA with an associated DSP processor or a farm of DSP processors.
While it is generally understood that DSP processors can be programmed in C – leading to a much simpler development flow – this advantage is quickly dissipated when the design has to be partitioned across either multiple DSP processors or between a DSP processor and a FPGA. The truth is that a single DSP processor lacks the performance to do the signal processing required by most infrastructure systems.
This then requires system designers to make a choice between using multiple DSP processors or a FPGA. The latter choice almost always results in the lowest system cost/power implementation.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
- Introduction to the Philips’ LPC 2100 ARM 7-based microcontroller – the first standard microcontroller to integrate ARM-7 – and the first to use Philips’ new Memory Acceleration Module
- Using PLDs for Algorithm Acceleration - Faster, Better, Cheaper
- C-Language techniques for FPGA acceleration of embedded software
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM