Introduction to the Philips’ LPC 2100 ARM 7-based microcontroller – the first standard microcontroller to integrate ARM-7 – and the first to use Philips’ new Memory Acceleration Module
Trevor martin gives a developer’s view of Philips’ LPC 2100 ARM 7-based microcontroller – the first standard microcontroller to integrate ARM-7 – and the first to use Philips’ new Memory Acceleration Module.
Since its inception the ARM7 core has primarily been available as an IP core for incorporation into custom System on chip designs. With the launch of the LPC2106 the first member of the LPC2100 family Philips has introduced a standard chip featuring the 32-bit ARM7 processor on chip FLASH and SRAM with a range of general purpose peripherals in low pin count packages. However this on it own does not necessarily make a successful microcontroller, as always the devil is in the detail and this article will look at some of the key features of the LPC2100 family that help to successfully integrate the ARM7 CPU into a standard microcontroller architecture.
Click here to read more ....
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Articles
- NoCs and the transition to multi-die systems using chiplets
- The Hitchhiker's Guide to Programming and Optimizing CXL-Based Heterogeneous Systems
- Connecting the Digital World - The Path to 224 Gbps Serial Links
- Stop-For-Top IP model to replace One-Stop-Shop by 2025... and support the creation of successful Chiplet business
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow