Repeatable results with design preservation
By Kate Kelley, Xilinx
pldesignline.com (June 08, 2010)
Increasingly, FPGA designs are no longer just the 'glue logic' of the past; they are becoming more complex every year, often incorporating challenging such as PCI Express cores.
The complex modules newer designs, even when not changing, can present difficulties when attempting to meet quality-of-result (QoR) requirements. Time spent trying to maintain timing in these modules is not only frustrating, but often unproductive as well.
The design preservation flow solves this issue by allowing the customer to meet timing on the critical module(s) of the design and then reuse the implementation results in future iterations. This reduces the number of implementation iterations in the timing closure phase of the design.
To read the full article, click here
Related Semiconductor IP
- DFI 6.0 Verification IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
Related Articles
- Preservation of Circuit Structure and Timing during Fault Emulation in FPGA
- Time-Domain Analog Design: Why and How
- Automotive Design Needs Efficient Verification to Survive
- VLSI Physical Design Methodology for ASIC Development with a Flavor of IP Hardening
Latest Articles
- Hardware Acceleration of Block-Diffusion LLM for Edge Devices
- Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency
- Hardware-managed heterogeneous high-bandwidth memory and flash in LLM inference systems
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node