Design considerations for power sensitive embedded devices
Adam Kaiser, Mentor Graphics
EETimes (4/17/2012 10:38 PM EDT)
The importance of power management and optimization in today’s embedded designs has been steadily growing as an increasing number of battery-powered devices continue to perform more complex tasks.
The unrelenting demand for connectivity and new features presents a growing challenge to designers. Yet, very often power optimizations are left to the very end of the project cycle, almost as an afterthought. When setting out to design a power-optimized embedded device, it is important to consider power management from the very inception of the project.
This article discusses design considerations that should be made when beginning a new embedded design. The considerations include choosing the hardware with appropriate capabilities, defining hardware design constraints to allow software to manage power, making the right choice of an operating system and drivers, defining appropriate power usage profiles, choosing measurable power goals, and providing these goals to the software development team to track throughout the development process.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Articles
- Deciphering phone and embedded security - Part 4: Ideal platform for next-generation embedded devices
- Memory solution addressing power and security problems in embedded designs
- Simplify the Internet of Things connectivity of embedded devices
- Power management in embedded software
Latest Articles
- ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs
- ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training
- OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
- CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
- CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST