Design considerations for integrated CMOS receivers
By Louis Fan Fei, Garmin International
RF Designline -- (10/12/07, 08:13:00 AM EDT)
To meet the demands for the multi-band, multi-mode wireless standards in the current market, a highly integrated wireless receiver (RX) is desired. CMOS technology has become the technology of choice for the integrated receiver design. CMOS's raw performance is not as good as SiGe or GaAs. But most of the baseband (BB) ICs are implemented with CMOS. Thus, it gives the advantage to CMOS in applications where a single chip that combines RF and BB IC is desired. The cost advantages of established CMOS manufacturing processes are also a factor to consider.
A traditional heterodyne RX converts the RF signal to the intermediate frequency (IF) stage. At every stage, various filters, such as surface acoustic wave (SAW) ones, are used to filter out the image signal, to select the channel, and to reduce the effects of any interfering signals. It is hard to achieve a fully-integrated receiver because of the required external components. Direct-conversion RX has become the dominant RX architecture. The well-known problems with a direct conversion RX like DC offset, high input second order intercept point (IIP2), and 1/f noise can be resolved with various correction loops in the BB and careful RFIC designs.
The major RX performance parameters are RX sensitivity, RX selectivity, dynamic range, IIP2, IIP3, and phase noise. The RX sensitivity is mostly set by the front end low noise amplifier (LNA) and the demodulator (DEMOD). The RX selectivity is determined by the on-chip low pass filter (LPF)'s rejection performance. Dynamic range, IIP2, and IIP3 are the measures of how robust a RX is with the presence of in-band and out-of-band interferences. Phase noise has a major impact on the signal modulation and demodulation as phase-shift key modulation is commonly used. This article thus will focus the major building blocks in the RX that influence receiver performance.
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