Data acquisition systems and SoCs - A guide
Asha Ganesan, Cypress
EDN (August 26, 2013)
Data acquisition systems (abbreviated with the acronym DAS or DAQ) measure real world signals (temperature, pressure, humidity etc.) by performing appropriate signal conditioning on a raw signal (amplification, level shifting, etc.), and then digitizing and storing these signals. This digital signals can then be transmit to another digital system for further processing, usually on a periodic basis.
Examples of data acquisition systems include such applications as weather monitoring, recording a seismograph, pressure, temperature and wind strength and direction. This information is fed to computers, which then predict natural events like rain and calamities like earthquakes and destructive winds. An example of a DAS in the medical field is a patient monitoring system that tracks signals like an ECG (Electro-cardiogram) or EEG (Electro-encephalogram).
A typical DAS consists of the following components:
- Sensors that convert real world phenomenon to equivalent electrical analog signals
- Signal conditioning circuitry that alters signals from the sensor to a form, which can be digitized
- Analog to digital converters that convert conditioned analog signals to a digital representation
- Store and forward memory, which is used to store digital signal streams for forwarding to another system at a later time
- A communication interface over which the digital streams are transferred to the other system
- A microprocessor system or a microcontroller to sequence and control all of the other components.
Figure 1 shows a block diagram of a basic data acquisition system. The details of these internal blocks are explained in the next section.
To read the full article, click here
Related Semiconductor IP
- Ultra Ethernet MAC & PCS 100G/200G/400G/800G
- Ethernet PCS 100G/200G/400G/800G/1.6T
- Ethernet MAC 100G/200G/400G/800G/1.6T
- Junction Over-Temperature Detector with Linear Centigrade-to-Voltage Output - X-FAB XT018
- Performance P570 Gen 3
Related Articles
- A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection
- A 16 nm 1.60TOPS/W High Utilization DNN Accelerator with 3D Spatial Data Reuse and Efficient Shared Memory Access
- Design trade-offs of using SAR and Sigma Delta Converters for Multiplexed Data Acquisition Systems
- From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
Latest Articles
- Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors
- TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
- Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
- A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
- ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits