Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
By Anh Kiet Pham 1, Van Truong Vo 2, Vu Trung Duong Le 1, Tuan Hai Vu 2,3, Hoai Luan Pham 1, Van Tinh Nguyen 4, and Yasuhiko Nakashima 1
1 Nara Institute of Science and Technology, 8916–5 Takayama-cho, Ikoma, Nara, 630-0192 Japan.
2 University of Information Technology, Ho Chi Minh City, 700000, Vietnam
3 Vietnam National University, Ho Chi Minh City, 700000, Vietnam
4 Le Quy Don Technical University, Ha Noi, Viet Nam.
Abstract
Cryptographic operations are critical for securing IoT, edge computing, and autonomous systems. However, current RISC-V platforms lack efficient hardware support for comprehensive cryptographic algorithm families and post-quantum cryptography. This paper presents Crypto-RV, a RISC-V co-processor architecture that unifies support for SHA-256, SHA-512, SM3, SHA3-256, SHAKE-128, SHAKE-256 AES-128, HARAKA-256, and HARAKA-512 within a single 64-bit datapath. Crypto-RV introduces three key architectural innovations: a high-bandwidth internal buffer (128x64-bit), cryptography-specialized execution units with four-stage pipelined datapaths, and a double-buffering mechanism with adaptive scheduling optimized for large-hash. Implemented on Xilinx ZCU102 FPGA at 160 MHz with 0.851 W dynamic power, Crypto-RV achieves 165 times to 1,061 times speedup over baseline RISC-V cores, 5.8 times to 17.4 times better energy efficiency compared to powerful CPUs. The design occupies only 34,704 LUTs, 37,329 FFs, and 22 BRAMs demonstrating viability for high-performance, energy-efficient cryptographic processing in resource-constrained IoT environments.
Index Terms — RISC-V, Cryptographic Accelerator, SHA 2/SHA-3, IoT, HARAKA
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